Verilog

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History

Prabhu Goel Phil Moorby S.Y.H. Su Gateway Design Automation Cadence Design Systems

19 related topics

Overview

Standardized Hardware description language Electronic systems Register-transfer level Analog circuits

31 related topics

Standards development

Doi ISBN Wayback Machine Backus-Naur form

4 related topics

Program Language Interface (PLI)

Deprecated Verilog Procedural Interface Test harnesses Instruction set simulators Microcontroller

6 related topics

Key facts & relationships

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Designed by: Prabhu Goel, Phil Moorby and Chi-Lai Huang
Developer: IEEE
Filename extensions: .v, .vh
First appeared: 1984 (1984)
Paradigm: Structured
Stable release: IEEE 1800-2023 / 6 December 2023; 2 years ago (2023-12-06)

Topics to explore

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Overview

Standardized
Hardware description language
Electronic systems Electronic system
Register-transfer level
Analog circuits Analogue electronics
Mixed-signal circuits Mixed-signal integrated circuit
Genetic circuits Synthetic biological circuit
SystemVerilog
Assignment operators Assignment operator
Temporary storage variables Temporary storage variable
Schematic capture
Simulate electronic circuits Electronic circuit simulation
C programming language C (programming language)
Software development
Case-sensitive
Preprocessor
Control flow
Keywords Keyword (computer programming)
Operator precedence
Hierarchy of modules
Bidirectional ports Bidirectional port
Concurrent Concurrency (computer science)
Statement blocks Statement block
Dataflow language
Synthesizable Logic synthesis
Netlist
FPGA
VLSI
Photo mask set Mask set
ASIC Application-specific integrated circuit

History

Prabhu Goel
Phil Moorby
S.Y.H. Su
Gateway Design Automation
Cadence Design Systems
Logic simulators Logic simulator
VHDL
Standardization
Accellera
IEEE
Verilog-A
Spectre Spectre Circuit Simulator
Verilog-AMS
EDA Electronic design automation
Hardware verification languages Hardware verification language
E language E (verification language)
Superlog Superlog HDL
Synopsys
Superset

Example

Flip-flops Flip-flop (electronics)
Counter Counter (digital)

Synthesizable constructs

Four-valued logic

Advanced semantic analysis

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Map overview Semantic statistics

Nodes85

Edges84

Triples189

Avg. degree1.98

Density0.023529

Components1

How this topic connects Entity context

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Verilog

Top relations

related to Standards development · 19

Verilog → April, Archived, Backus-Naur, CS1, IEEE P1364, IEEE P1800, IEEE Standard, IEEE STD, IEEE-1364, IEEESTD, ISBN, March, Revision, SystemVerilog, The, This, Verilog Hardware Description Language, Wayback Machine, Working

related to System tasks · 17

Verilog → All, Close, Declare, Extended-VCD, I/O, It, Open, Print, Read, Return, System, This, Turn, Value, Value Change Dump, VCD, Verilog-2001

related to Beginning · 16

Verilog → Automated Integrated Design Systems, Cadence, Cadence Design Systems, Chi-Lai Huang, Gateway Design Automation, Gateway's Verilog, HDL-simulator, LALSD, Originally, PhD, Phil Moorby, Prabhu Goel, Professor, Su, The, Verilog-XL

related to Verilog 2001 · 15

Verilog → And, Boolean, C-style, Extensions, File I/O, First, IEEE, IEEE Standard, Previously, The, These, Using, Verilog-2001, Verilog-95, VHDL's

related to SystemVerilog · 14

Verilog → Accellera, As, Co-Design Automation Inc, IEEE, IEEE Standard, OpenVera, P1800-2005, Superlog, Synopsys, SystemVerilog, The, Vera, Verilog-2005, Verisity's

related to Verilog-95 · 13

Verilog → Accellera, Cadence, IEEE, IEEE Standard, In, Open Verilog International, OVI, Spectre, Verilog-95, Verilog-A, Verilog-AMS, VHDL, With

related to overview · 11

Verilog → ANSI C/C, At, Hardware, In, Its, Like, Since, Syntactic, The, There, Verilog's

related to Similar languages · 11

Verilog → AMS, Hardware, HDL, Modeling, Open-source, Scala, Specification Language, SystemVerilog, Temporal, Verilog-A, VHDL

related to Additional material · 10

Verilog → APIVerilog Procedural Interface, Direct Programming Interface, DPI, Hardware, HDL, List, Software, System-level, VPI, Waveform

related to Initial and always · 7

Verilog → Both, In, It, Once, The, There, These

Important terminology Word statistics

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Important terminology

ieee language always systemverilog standard value used set example logic reset hardware description initial time block design file software assignment

Entity relationships Subject–Predicate–Object triples

Subject	Predicate	Object	Confidence	Src
Verilog	Designed by	Prabhu Goel, Phil Moorby and Chi-Lai Huang	1.00	infobox
Verilog	Developer	IEEE	1.00	infobox
Verilog	Filename extensions	.v, .vh	1.00	infobox
Verilog	First appeared	1984 (1984)	1.00	infobox
Verilog	Paradigm	Structured	1.00	infobox
Verilog	Stable release	IEEE 1800-2023 / 6 December 2023; 2 years ago (2023-12-06)	1.00	infobox
Verilog	Typing discipline	Static, weak	1.00	infobox
Verilog	Website	https://ieeexplore.ieee.org/document/10458102	1.00	infobox
Verilog	is a	portmanteau of the words	0.90	text
Verilog use software-like syntax	instance of	OverviewHardware description languages	0.80	text
but unlike software programming languages they model physical hardware	instance of	OverviewHardware description languages	0.80	text
including concurrent operation	instance of	OverviewHardware description languages	0.80	text

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