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Hardware description language

In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, usually to design application-specific integrated circuits (ASICs) and to program field-programmable gate arrays (FPGAs).

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Overview

Motivation

Structure of HDL

History

Design using HDL

Simulating and debugging HDL code

Design verification with HDLs

HDL and programming languages

High-level synthesis

Examples of HDLs

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Hardware description language

Nodes130
Edges129
Triples63
Avg. degree1.98
Density0.015385
Components1

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Hardware description language

Top relations

related to history · 17
Hardware description language → Allen Newell's, At, Computer Structures, DEC, DEC's PDP-16 RT-Level Modules, Digital Equipment Corporation, Gordon Bell, ISP, ISPL, ISPS, NATO, North Atlantic Treaty Organization, PDP-8, RTMs, The, This, US
see also · 14
Hardware description language → American, Bluespec, C-like, Conversion, Formal, Hardware, HDL, HDLModeling, Notation, Programming, Specification Language, System-level, Temporal, Tools
related to Motivation · 11
Hardware description language → CMOS, Due, ECL, Example, HDLs, In, Moore's, TTL, Two, Verilog, VHDL
related to Comparison with control-flow languages · 9
Hardware description language → Before, Digital, Generally, HDL, It, Synthesizers, System Verilog, The, Using

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Important terminology

hdl design hardware language description hdls languages programming circuit simulation synthesis vhdl verilog used electronic logic model code using also

Entity relationships Subject–Predicate–Object triples

SubjectPredicateObjectConfidenceSrc
C or ALGOLinstance ofwhich can then be placed and routed to produce the set of masks used to create an integrated circuit.A hardware description language looks much like a programming language0.80text
a Cinstance ofoften beginning with a high-level algorithmic description0.80text
Perl to automatically generate repetitive circuit structures in the HDL languageinstance ofDesigners often use scripting languages0.80text
Cadenceinstance ofcreating a sub-field called high-level synthesis.Companies0.80text
Synopsysinstance ofcreating a sub-field called high-level synthesis.Companies0.80text
Agility Design Solutions are promoting SystemC as a way to combine high-level languages with concurrency models to allow faster design cycles for field-programmable gate arraysinstance ofcreating a sub-field called high-level synthesis.Companies0.80text
SystemVeriloginstance ofInc.'s CoreFire Design Suite and National Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design entry and languages0.80text
SystemVHDLinstance ofInc.'s CoreFire Design Suite and National Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design entry and languages0.80text
and Handel-C seek to accomplish the same goalinstance ofInc.'s CoreFire Design Suite and National Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design entry and languages0.80text
but are aimed at making existing hardware engineers more productiveinstance ofInc.'s CoreFire Design Suite and National Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design entry and languages0.80text
rather than making FPGAs more accessible to existing software engineers.It is also possible to design hardware modules using MATLABinstance ofInc.'s CoreFire Design Suite and National Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design entry and languages0.80text
Simulink using the MathWorks HDL Coder tool or DSP Builder for Intel FPGAs or Xilinx System Generatorinstance ofInc.'s CoreFire Design Suite and National Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design entry and languages0.80text

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