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Logic synthesis

In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool. Common examples of this process include synthesis of designs specified in…

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Overview

History

Commercial tools

Logic elements

Multi-level logic minimization

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Map overview Semantic statistics

Logic synthesis

Nodes54
Edges53
Triples140
Avg. degree1.96
Density0.037037
Components1

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Logic synthesis

Top relations

related to Further reading · 85
Logic synthesis → Alain, Archived, ASIC, Astola, August, Burgun, Business Media, Chang, Chapter, Cheng, Cite, CiteSeerX, Consistent Approach, Decomposition, Department, Devadas, Electrical Engineering, Electronic, Fabio, Finland
related to history · 19
Logic synthesis → Another, Bell Labs, Boolean, Claude Shannon, Espresso, FSMs, George Boole, Hence, IBM, In, Karnaugh, McCluskey, Nowadays, PLA, PLAs, Quine, The, The Karnaugh, This
related to High-level or behavioral · 12
Logic synthesis → ALUs, ANSI C/C, ASIC, ESL, FPGA, RTL, SystemC, These, Using, Verilog, VHDL, With
related to References · 12
Logic synthesis → Chapter, Electronic, Electronic Design Automation For, Integrated Circuits Handbook, ISBN, Lavagno, Martin, Narendra Shenoy, Scheffer, Sunil Khatri, The, Volume
related to Commercial tools · 8
Logic synthesis → Cadence, Cadence First Encounter, Siemens, Siemens Precision RTL, Synopsys, Synopsys Design Compiler, The, Their
is a · 1
Logic synthesis → process by which an abstract specification of desired circuit behavior

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Important terminology

logic synthesis design circuit rtl electronic automation minimization tools circuits description step verification isbn boolean research used technology tool others

Entity relationships Subject–Predicate–Object triples

SubjectPredicateObjectConfidenceSrc
Logic synthesisis aprocess by which an abstract specification of desired circuit behavior0.90text
PALs or FPGAsinstance ofSome synthesis tools generate bitstreams for programmable logic devices0.80text
while others target the creation of ASICsinstance ofSome synthesis tools generate bitstreams for programmable logic devices0.80text
the available gatesinstance ofMapping is constrained by factors0.80text
Logic synthesisrelated to Commercial toolsThe0.60section
Logic synthesisrelated to Commercial toolsSynopsys0.60section
Logic synthesisrelated to Commercial toolsCadence0.60section
Logic synthesisrelated to Commercial toolsSiemens0.60section
Logic synthesisrelated to Commercial toolsTheir0.60section
Logic synthesisrelated to Commercial toolsSynopsys Design Compiler0.60section
Logic synthesisrelated to Commercial toolsCadence First Encounter0.60section
Logic synthesisrelated to Commercial toolsSiemens Precision RTL0.60section

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