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Instruction set simulator

An instruction set simulator (ISS) is a simulation model, usually coded in a high-level programming language, which mimics the behavior of a mainframe or microprocessor by "reading" instructions and maintaining internal variables which represent the processor's registers.

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Instruction set simulator

Nodes56
Edges55
Triples27
Avg. degree1.96
Density0.035714
Components1

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Instruction set simulator

Top relations

see also · 22
Instruction set simulator → Allows, ARM, ARM-based, Computer, CPU, CPU-OS Simulator, HP, I/O, Integrated RISC, Intel, INTERP/80, Java-based, Little, PDP-11, PIC, RPL, Saturn, Saturn CPU, Sim, Simh

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Important terminology

instruction program simulation hardware set simulator monitoring pseudo memory iss instructions registers system simulators test code one target location execution

Entity relationships Subject–Predicate–Object triples

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SubjectPredicateObjectConfidenceSrc
timersinstance ofIt is sometimes integrated with simulated peripheral circuits0.80text
interruptsinstance ofIt is sometimes integrated with simulated peripheral circuits0.80text
serial portsinstance ofIt is sometimes integrated with simulated peripheral circuits0.80text
general I/O portsinstance ofIt is sometimes integrated with simulated peripheral circuits0.80text
etc. to mimic the behavior of a microcontroller.The basic instruction simulation technique is the same regardless of purposeinstance ofIt is sometimes integrated with simulated peripheral circuits0.80text
Instruction set simulatorsee alsoSimulators ARMulator0.60section
Instruction set simulatorsee alsoCPU0.60section
Instruction set simulatorsee alsoARM0.60section
Instruction set simulatorsee alsoComputer0.60section
Instruction set simulatorsee alsoSim0.60section
Instruction set simulatorsee alsoJava-based0.60section
Instruction set simulatorsee alsoPIC0.60section

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