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SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.
History & Measurement
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instructions sh-2 instruction 32-bit hitachi sh-4 core used risc 16-bit architecture cpu also sh-5 memory sh-3 design renesas sh-2a register
| Subject | Predicate | Object | Confidence | Src |
|---|---|---|---|---|
| SuperH | Bits | 32-bit (32 → 64) | 1.00 | infobox |
| SuperH | Design | RISC | 1.00 | infobox |
| SuperH | Designer | Hitachi | 1.00 | infobox |
| SuperH | Encoding | SH-2: 16-bit instructions SH-2A and newer: mixed 16- and 32-bit instructions | 1.00 | infobox |
| SuperH | Endianness | Bi | 1.00 | infobox |
| SuperH | Introduced | 1992 | 1.00 | infobox |
| SuperH | Open | Yes, and royalty-free (reverse-engineered after patents expired) | 1.00 | infobox |
| ARM or MIPS important for cache | instance of | High code density compared to other 32-bit RISC ISAs | 0.80 | text |
| memory bandwidth performanceExisting compiler | instance of | High code density compared to other 32-bit RISC ISAs | 0.80 | text |
| operating system support | instance of | High code density compared to other 32-bit RISC ISAs | 0.80 | text |
| the Jornada | instance of | used for mobile and handheld applications | 0.80 | text |
| strong in Windows CE applications | instance of | used for mobile and handheld applications | 0.80 | text |
These clusters group vocabulary that occurs around closely connected concepts in the source material.
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