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Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and wire.
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delay used calculation wire gate circuit elmore methods output called accurate tables simple moment matching design delays logic may method
| Subject | Predicate | Object | Confidence | Src |
|---|---|---|---|---|
| Delay calculation | is a | term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it | 0.90 | text |
| SPICE may be used | instance of | Circuit simulators | 0.80 | text |
| logic synthesis | instance of | method.Two dimensional tables are commonly used in applications | 0.80 | text |
| placement | instance of | method.Two dimensional tables are commonly used in applications | 0.80 | text |
| routing | instance of | method.Two dimensional tables are commonly used in applications | 0.80 | text |
| PRIMA | instance of | Newer methods | 0.80 | text |
| PVL use implicit moment matching | instance of | Newer methods | 0.80 | text |
| based on Krylov subspaces | instance of | Newer methods | 0.80 | text |
| SPICE may be used | instance of | Compared to circuit simulation they are faster but less accurate.Circuit simulators | 0.80 | text |
| NAND | instance of | the blocks are logic gates | 0.80 | text |
| OR | instance of | the blocks are logic gates | 0.80 | text |
| AND | instance of | the blocks are logic gates | 0.80 | text |
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