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Logical effort

The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function (including the number of stages necessary) and sizing gates to achieve the minimum delay possible for a circuit.

Derivation of delay in a logic gate, Examples & Procedure for calculating the logical effort of a single stage

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Derivation of delay in a logic gate

Fanout of 4Logic gateParasitic delayStage effort
4 related topics

Examples

Elmore delayNAND gateNOR gate
3 related topics

Procedure for calculating the logical effort of a single stage

PFET resistance
1 related topics

Overview

Ivan SutherlandBob SproullEstimate delayCMOS
4 related topics

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Derivation of delay in a logic gate

Procedure for calculating the logical effort of a single stage

Examples

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Logical effort

Nodes17
Edges16
Triples27
Avg. degree1.88
Density0.117647
Components1

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Logical effort

Top relations

related to Further reading · 16
Logical effort → Circuits, CMOS VLSI Design, David, Designing Fast CMOS Circuits, Ed, Harris, ISBN, Ivan, Morgan Kaufmann, Neil, Pearson/Addison-Wesley, Robert, Sproull, Sutherland, Systems Perspective, Weste
related to Delay in NAND and NOR gates · 6
Logical effort → Due, For, NAND, NOR, Similarly, The
related to Delay in an inverter · 4
Logical effort → By, Elmore, If, The
related to Multistage logic networks · 1
Logical effort → The

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Important terminology

effort gate delay logical inverter gates normalized equal stage input driving capacitance output circuit nand minimum cmos load electrical drive

Entity relationships Subject–Predicate–Object triples

SubjectPredicateObjectConfidenceSrc
Logical effortrelated to Delay in an inverterBy0.60section
Logical effortrelated to Delay in an inverterIf0.60section
Logical effortrelated to Delay in an inverterThe0.60section
Logical effortrelated to Delay in an inverterElmore0.60section
Logical effortrelated to Delay in NAND and NOR gatesThe0.60section
Logical effortrelated to Delay in NAND and NOR gatesNAND0.60section
Logical effortrelated to Delay in NAND and NOR gatesSimilarly0.60section
Logical effortrelated to Delay in NAND and NOR gatesNOR0.60section
Logical effortrelated to Delay in NAND and NOR gatesDue0.60section
Logical effortrelated to Delay in NAND and NOR gatesFor0.60section
Logical effortrelated to Further readingSutherland0.60section
Logical effortrelated to Further readingIvan0.60section

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