ARM Cortex-A73

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Explore the main themes, entities and connections around ARM Cortex-A73. Start with the topic map, then use the sections below for research and deeper semantic analysis.

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Products

Kirin 960 Big.LITTLE Cortex-A53 MediaTek Cortex-A35

9 related topics

Licensing

SIP core GPU Display controller DSP Image processor

8 related topics

Design

32-bit ARMv7-A Cortex-A17 Mobile computing Integer

7 related topics

Overview

Central processing unit ARMv8-A Instruction set ARM Holdings Sophia

9 related topics

Key facts & relationships

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Application: Mobile
Cores: 1–4 per cluster, multiple clusters
Designed by: ARM Holdings
Instruction set: ARMv8-A
L1 cache: 96–128 KiB (64 KiB I-cache with parity, 32–64 KiB D-cache) per core
L2 cache: 1–8 MiB

Topics to explore

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Overview

Design

32-bit
ARMv7-A
Cortex-A17 ARM Cortex-A17
Mobile computing
Integer
Instructions per clock (IPC) Instructions per clock
Floating point

Licensing

SIP core Semiconductor intellectual property core
GPU Graphics processing unit
Display controller
DSP Digital signal processor
Image processor
Die Die (integrated circuit)
System on a chip
Kryo 280 Kryo (microarchitecture)

Products

Kirin 960 HiSilicon
Big.LITTLE ARM big.LITTLE
Cortex-A53 ARM Cortex-A53
MediaTek
Cortex-A35 ARM Cortex-A35
Qualcomm
Snapdragon Qualcomm Snapdragon
Samsung
Exynos

Advanced semantic analysis

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Map overview Semantic statistics

Nodes38

Edges37

Triples16

Avg. degree1.95

Density0.052632

Components1

How this topic connects Entity context

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ARM Cortex-A73

Top relations

Application · 1

ARM Cortex-A73 → Mobile

Cores · 1

ARM Cortex-A73 → 1–4 per cluster, multiple clusters

Designed by · 1

ARM Cortex-A73 → ARM Holdings

Instruction set · 1

ARM Cortex-A73 → ARMv8-A

L1 cache · 1

ARM Cortex-A73 → 96–128 KiB (64 KiB I-cache with parity, 32–64 KiB D-cache) per core

L2 cache · 1

ARM Cortex-A73 → 1–8 MiB

L3 cache · 1

ARM Cortex-A73 → None

Launched · 1

ARM Cortex-A73 → 2016

Max. CPU clock rate · 1

ARM Cortex-A73 → to 2.8 GHz

Predecessors · 1

ARM Cortex-A73 → ARM Cortex-A72 ARM Cortex-A17

Important terminology Word statistics

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Important terminology

cortex-a73 cores arm cortex-a72 design core designed armv8-a kryo 280 also ghz successor big little cortex-a53 clock instruction set though

Entity relationships Subject–Predicate–Object triples

Subject	Predicate	Object	Confidence	Src
ARM Cortex-A73	Application	Mobile	1.00	infobox
ARM Cortex-A73	Cores	1–4 per cluster, multiple clusters	1.00	infobox
ARM Cortex-A73	Designed by	ARM Holdings	1.00	infobox
ARM Cortex-A73	Instruction set	ARMv8-A	1.00	infobox
ARM Cortex-A73	L1 cache	96–128 KiB (64 KiB I-cache with parity, 32–64 KiB D-cache) per core	1.00	infobox
ARM Cortex-A73	L2 cache	1–8 MiB	1.00	infobox
ARM Cortex-A73	L3 cache	None	1.00	infobox
ARM Cortex-A73	Launched	2016	1.00	infobox
ARM Cortex-A73	Max. CPU clock rate	to 2.8 GHz	1.00	infobox
ARM Cortex-A73	Predecessors	ARM Cortex-A72 ARM Cortex-A17	1.00	infobox
ARM Cortex-A73	Product code name	Artemis	1.00	infobox
ARM Cortex-A73	Successor	ARM Cortex-A75	1.00	infobox
ARM Cortex-A73	is a	central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Sophia design centre	0.90	text

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Min side: 3