ARM Cortex-A17

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Overview

ARMv7-A architecture ARM Holdings Cache-coherent Cortex-A9 ARM Cortex-A12

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Key facts & relationships

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Cores: 1–4, can be combined with less powerful A7 cores in a big.LITTLE configuration
Designed by: ARM Holdings
Instruction set: ARMv7-A
L1 cache: 32–64 KiB instruction · 32 KiB data
L2 cache: 256 KiB–8 MiB (configurable L2 cache controller)
Max. CPU clock rate: 1.25 GHz to 2.75 GHz

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Overview

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Map overview Semantic statistics

Nodes15

Edges14

Triples9

Avg. degree1.87

Density0.133333

Components1

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ARM Cortex-A17

Top relations

L1 cache · 2

ARM Cortex-A17 → 32 KiB data, 32–64 KiB instruction

Cores · 1

ARM Cortex-A17 → 1–4, can be combined with less powerful A7 cores in a big.LITTLE configuration

Designed by · 1

ARM Cortex-A17 → ARM Holdings

Instruction set · 1

ARM Cortex-A17 → ARMv7-A

L2 cache · 1

ARM Cortex-A17 → 256 KiB–8 MiB (configurable L2 cache controller)

Max. CPU clock rate · 1

ARM Cortex-A17 → 1.25 GHz to 2.75 GHz

Predecessors · 1

ARM Cortex-A17 → ARM Cortex-A12 ARM Cortex-A9

is a · 1

ARM Cortex-A17 → 32-bit processor core implementing the ARMv7-A architecture

Important terminology Word statistics

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Important terminology

arm cortex-a17 cortex-a9 core cortex-a12 architecture armv7-a cores performance features also holdings big little data instruction cache-coherent virtualization neon floating-point

Entity relationships Subject–Predicate–Object triples

Subject	Predicate	Object	Confidence	Src
ARM Cortex-A17	Cores	1–4, can be combined with less powerful A7 cores in a big.LITTLE configuration	1.00	infobox
ARM Cortex-A17	Designed by	ARM Holdings	1.00	infobox
ARM Cortex-A17	Instruction set	ARMv7-A	1.00	infobox
ARM Cortex-A17	L1 cache	32–64 KiB instruction	1.00	infobox
ARM Cortex-A17	L1 cache	32 KiB data	1.00	infobox
ARM Cortex-A17	L2 cache	256 KiB–8 MiB (configurable L2 cache controller)	1.00	infobox
ARM Cortex-A17	Max. CPU clock rate	1.25 GHz to 2.75 GHz	1.00	infobox
ARM Cortex-A17	Predecessors	ARM Cortex-A12 ARM Cortex-A9	1.00	infobox
ARM Cortex-A17	is a	32-bit processor core implementing the ARMv7-A architecture	0.90	text

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