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ARC (processor)

Argonaut RISC Core (ARC) is a family of 32-bit and 64-bit reduced instruction set computer (RISC) central processing units (CPUs) originally designed by ARC International.

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Key facts & relationships

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Bits
32-bit, 64-bit
Branching
Compare and branch
Design
RISC
Designer
ARC International PLC
Encoding
Variable (16- and 32-bit)
Endianness
Bi

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Overview

History

Design configuration

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Map overview Semantic statistics

ARC (processor)

Nodes33
Edges32
Triples13
Avg. degree1.94
Density0.060606
Components1

How this topic connects Entity context

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ARC (processor)

Top relations

Bits · 1
ARC (processor) → 32-bit, 64-bit
Branching · 1
ARC (processor) → Compare and branch
Design · 1
ARC (processor) → RISC
Designer · 1
ARC (processor) → ARC International PLC
Encoding · 1
ARC (processor) → Variable (16- and 32-bit)
Endianness · 1
ARC (processor) → Bi
Extensions · 1
ARC (processor) → APEX user-defined instructions
Introduced · 1
ARC (processor) → 1996; 30 years ago (1996)
Type · 1
ARC (processor) → Load–store
Version · 1
ARC (processor) → ARCv3

Important terminology Word statistics

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Important terminology

arc argonaut processors processor 32-bit international synopsys performance instruction set 64-bit including design development projects soc applications risc configuration embedded

Entity relationships Subject–Predicate–Object triples

SubjectPredicateObjectConfidenceSrc
ARC (processor)Bits32-bit, 64-bit1.00infobox
ARC (processor)BranchingCompare and branch1.00infobox
ARC (processor)DesignRISC1.00infobox
ARC (processor)DesignerARC International PLC1.00infobox
ARC (processor)EncodingVariable (16- and 32-bit)1.00infobox
ARC (processor)EndiannessBi1.00infobox
ARC (processor)ExtensionsAPEX user-defined instructions1.00infobox
ARC (processor)Introduced1996; 30 years ago (1996)1.00infobox
ARC (processor)TypeLoad–store1.00infobox
ARC (processor)VersionARCv31.00infobox
BRenderinstance ofstarted reducing ATL projects0.80text
motion captureinstance ofstarted reducing ATL projects0.80text

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    Min side: 3
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