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Test compression

Test compression is a technique used to reduce the time and cost of testing integrated circuits. The first ICs were tested with test vectors created by hand. It proved very difficult to get good coverage of potential faults, so Design for testability (DFT) based on scan and automatic test pattern generation (ATPG) were developed to explicitly test each…

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Integrated circuits Design for testability Automatic test pattern generation Scan chain Compactor

5 related topics

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Test compression

Nodes7

Edges6

Triples6

Avg. degree1.71

Density0.285714

Components1

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Test compression

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related to External links · 5

Test compression → Abstract, Electronic Design Automation, IEEE, IEEE Council, This

is a · 1

Test compression → technique used to reduce the time and cost of testing integrated circuits

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Important terminology

test scan compression time vectors data internal design tester values number chains decompressor compactor used reduce cost testing circuits tested

Entity relationships Subject–Predicate–Object triples

Subject	Predicate	Object	Confidence	Src
Test compression	is a	technique used to reduce the time and cost of testing integrated circuits	0.90	text
Test compression	related to External links	Abstract	0.60	section
Test compression	related to External links	IEEE	0.60	section
Test compression	related to External links	IEEE Council	0.60	section
Test compression	related to External links	Electronic Design Automation	0.60	section
Test compression	related to External links	This	0.60	section

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