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Multiple patterning

Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide…

Directed self-assembly (DSA), Other multi-patterning techniques & Industrial adoption

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Directed self-assembly (DSA)

CopolymersDegree of polymerizationMonomerSquare rootLogarithm
6 related topics

Other multi-patterning techniques

Cost reductionMoore's LawEUVIon implantationIon beam
5 related topics

Industrial adoption

7nm7 nm5 nmFinFETsSiCarrier
5 related topics

Situations requiring multiple patterning

Numerical apertureEUVDRAMIllumination
4 related topics

Topics to explore

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Overview

Situations requiring multiple patterning

Pitch splitting

Sidewall image transfer

Spacer-is-dielectric (SID) SADP

Directed self-assembly (DSA)

Other multi-patterning techniques

EUV multiple patterning possibilities

Multipatterning implementations

Industrial adoption

Advanced semantic analysis

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Map overview Semantic statistics

Multiple patterning

Nodes53
Edges52
Triples104
Avg. degree1.96
Density0.037736
Components1

How this topic connects Entity context

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Multiple patterning

Top relations

has method · 9
Multiple patterning → DUV, Especially, EUV, For, Grid, IMEC, Multiple, SADP/SAQP, Vias
related to Multiple patterning specific issues · 9
Multiple patterning → Consequently, Current, Cut, In, LELE, Multiple, SADP, SAQP, Where
related to Pitch splitting · 9
Multiple patterning → By, Consequently, For, It, LELE, Litho-Etch-Litho-Etch, The, This, When
related to DRAM · 8
Multiple patterning → Crossed, DRAM, Even, Furthermore, Like NAND Flash, Samsung, Stitched, When
related to Multipatterning implementations · 8
Multiple patterning → Current EUV, DRAM, EUV, For, Furthermore, Memory, NAND, These
related to Complementary polarity exposures · 7
Multiple patterning → IMEC, Instead, M0A, Neither, SRAM, The, This
related to EUV Multipatterning · 6
Multiple patterning → EUV, First, In, T2T, This, When
related to Leading-edge logic/ASIC multi-patterning practices · 6
Multiple patterning → EUV, Even, For, Only, Samsung, TSMC's
related to Other multi-patterning techniques · 6
Multiple patterning → EUV, LELELE, Moore's Law, Moreover, Some, There
related to Wafer productivity · 6
Multiple patterning → EUV, Multiple, Normalized WPM, Note, WPH, WPM

Important terminology Word statistics

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Important terminology

patterning euv nm pitch exposure pattern multiple may spacer line feature mask patterns also cut features single illumination two lines

Entity relationships Subject–Predicate–Object triples

SubjectPredicateObjectConfidenceSrc
by Intel for line-cutting at its 45 nm node or TSMC at its 28 nm nodeinstance ofextra masks have been implemented for better patterning quality0.80text
self alignment double patterninginstance ofSince then several double patterning techniques have been developed0.80text
chemical shrinksinstance ofThe feature size reduction will most likely require the assistance of techniques0.80text
thermal reflowinstance ofThe feature size reduction will most likely require the assistance of techniques0.80text
or shrink assist filmsinstance ofThe feature size reduction will most likely require the assistance of techniques0.80text
Multiple patterninghas methodMultiple0.60section
Multiple patterninghas methodEUV0.60section
Multiple patterninghas methodEspecially0.60section
Multiple patterninghas methodIMEC0.60section
Multiple patterninghas methodFor0.60section
Multiple patterninghas methodSADP/SAQP0.60section
Multiple patterninghas methodDUV0.60section

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