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X86 debug register

On the x86 architecture, a debug register is a register used by a processor for program debugging. There are six debug registers, named DR0...DR7, with DR4 and DR5 as obsolete synonyms for DR6 and DR7. The debug registers allow programmers to selectively enable various debug conditions associated with a set of four debug addresses. Two of these registers…

DR0 to DR3, DR4 and DR5 & DR6 - Debug status

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DR0 to DR3

RegistersLinear addressBreakpointPagingPhysical addresses
6 related topics

DR4 and DR5

CR4.DEPentiumOpcode
3 related topics

DR6 - Debug status

Status register
1 related topics

Overview

X86 architectureProgramDebuggingPrivilege levelGeneral protection fault
5 related topics

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DR0 to DR3

DR6 - Debug status

DR4 and DR5

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X86 debug register

Nodes20
Edges19
Triples0
Avg. degree1.9
Density0.1
Components1

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Important terminology

debug registers register conditions used dr7 dr4 address bits enable dr6 control breakpoint paging enabled addresses dr5 linear task global

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