ARM Cortex-A9

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Explore the main themes, entities and connections around ARM Cortex-A9. Start with the topic map, then use the sections below for research and deeper semantic analysis.

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Chips

System on a chip Altera FPGA AMLogic Apple A5

31 related topics

Features

Out-of-order Speculative issue Superscalar Pipeline DMIPS

14 related topics

Key facts & relationships

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Cores: 1–4
Designed by: ARM Holdings
Instruction set: ARMv7-A
L1 cache: 32 KB I, 32 KB D
L2 cache: 128 KB–8 MB (configurable with L2sr1 cache controller)
Launched: 2007

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Features

Out-of-order Out-of-order execution
Speculative issue Speculative execution
Superscalar
Pipeline Instruction pipeline
DMIPS Dhrystone
NEON ARM NEON
SIMD
Thumb-2
TrustZone
Jazelle
Jazelle RCT
TSMC 40G 45 nm process
65 nanometer (nm) 65 nm process
28 nm 28 nm process

Chips

Advanced semantic analysis

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Map overview Semantic statistics

Nodes48

Edges47

Triples20

Avg. degree1.96

Density0.041667

Components1

How this topic connects Entity context

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ARM Cortex-A9

Top relations

related to External links · 11

ARM Cortex-A9 → ARM Assembly, CISC, Cortex-A9 Technical Reference Manuals, Cortex-A9Popular ARM Cortex-A9 MPCore, Multi-core, Official, OMAP4440, SPEAr1310 Data, The ARM Cortex-A9 ProcessorsRISC, White, YouTube

Cores · 1

ARM Cortex-A9 → 1–4

Designed by · 1

ARM Cortex-A9 → ARM Holdings

Instruction set · 1

ARM Cortex-A9 → ARMv7-A

L1 cache · 1

ARM Cortex-A9 → 32 KB I, 32 KB D

L2 cache · 1

ARM Cortex-A9 → 128 KB–8 MB (configurable with L2sr1 cache controller)

Launched · 1

ARM Cortex-A9 → 2007

Max. CPU clock rate · 1

ARM Cortex-A9 → 2 GHz (typical) 3.1 GHz (proof-of-concept)

Predecessor · 1

ARM Cortex-A9 → ARM Cortex-A8

Successor · 1

ARM Cortex-A9 → ARM Cortex-A12

Important terminology Word statistics

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Important terminology

arm cortex-a9 instruction set cores multi-core chip ghz mediatek core execution mpcore processor architecture cpu features neon jazelle stmicroelectronics including

Entity relationships Subject–Predicate–Object triples

Subject	Predicate	Object	Confidence	Src
ARM Cortex-A9	Cores	1–4	1.00	infobox
ARM Cortex-A9	Designed by	ARM Holdings	1.00	infobox
ARM Cortex-A9	Instruction set	ARMv7-A	1.00	infobox
ARM Cortex-A9	L1 cache	32 KB I, 32 KB D	1.00	infobox
ARM Cortex-A9	L2 cache	128 KB–8 MB (configurable with L2sr1 cache controller)	1.00	infobox
ARM Cortex-A9	Launched	2007	1.00	infobox
ARM Cortex-A9	Max. CPU clock rate	2 GHz (typical) 3.1 GHz (proof-of-concept)	1.00	infobox
ARM Cortex-A9	Predecessor	ARM Cortex-A8	1.00	infobox
ARM Cortex-A9	Successor	ARM Cortex-A12	1.00	infobox
ARM Cortex-A9	related to External links	Official	0.60	section
ARM Cortex-A9	related to External links	Cortex-A9 Technical Reference Manuals	0.60	section
ARM Cortex-A9	related to External links	White	0.60	section

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