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The ARM Cortex-A55 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A55 is a two-wide decode in-order superscalar pipeline.
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cortex-a55 arm designed cores design core soc successor armv8 2-a instruction set a53 also used rockchip rk3566 cpu cortex-a53 cambridge
| Subject | Predicate | Object | Confidence | Src |
|---|---|---|---|---|
| ARM Cortex-A55 | Application | Mobile | 1.00 | infobox |
| ARM Cortex-A55 | Cores | 1–8 per cluster, multiple clusters | 1.00 | infobox |
| ARM Cortex-A55 | Designed by | ARM Holdings | 1.00 | infobox |
| ARM Cortex-A55 | Instruction set | ARMv8.2-A | 1.00 | infobox |
| ARM Cortex-A55 | L1 cache | 32–128 KB (16–64 KB I-cache with parity, 16–64 KB D-cache) per core | 1.00 | infobox |
| ARM Cortex-A55 | L2 cache | 64–256 KB | 1.00 | infobox |
| ARM Cortex-A55 | L3 cache | 512 KB – 4 MB | 1.00 | infobox |
| ARM Cortex-A55 | Launched | 2017 | 1.00 | infobox |
| ARM Cortex-A55 | Max. CPU clock rate | 1.25 GHz to 2.31 GHz | 1.00 | infobox |
| ARM Cortex-A55 | Predecessor | ARM Cortex-A53 | 1.00 | infobox |
| ARM Cortex-A55 | Product code name | Ananke | 1.00 | infobox |
| ARM Cortex-A55 | Successor | ARM Cortex-A510 | 1.00 | infobox |
| ARM Cortex-A55 | is a | central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre | 0.90 | text |
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