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Universal Verification Methodology

The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e verification language developed by Verisity Design in 2001. The UVM class library brings a…

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AccelleraStandards organizationElectronic design automationCadence Design SystemsMentor Graphics
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Official

IEEESynopsysNvidia
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FactoryObject
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  • Factory Factory (object-oriented programming)
  • Object Object (computer science)

Official

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Universal Verification Methodology

Nodes22
Edges21
Triples19
Avg. degree1.91
Density0.090909
Components1

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Universal Verification Methodology

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related to Official · 14
Universal Verification Methodology → Accellera1800, Cadence Design Systems, Class Reference, IEEE, IEEE Standard, Mentor Graphics, Nvidia, Reference Manual, September, Superseded, Synopsys, Universal Verification Methodology Language, UVM, Working Group

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uvm class dut verification component design object scoreboard agent language accellera may methodology factory used implemented cadence mentor graphics developed

Entity relationships Subject–Predicate–Object triples

SubjectPredicateObjectConfidenceSrc
sequencesinstance ofThe UVM class library brings a framework and automation to the SystemVerilog language0.80text
data automation featuresinstance ofThe UVM class library brings a framework and automation to the SystemVerilog language0.80text
mode bits or portions of the environment registersVerification component settings that can not be altered during simulationScoreboardDescriptionA scoreboard can be implemented in various waysinstance ofsuch as power and high-impedanceRegister settings that can not be altered during simulation0.80text
mode bits or portions of the environment registersVerification component settings that can not be altered during simulation InitializationIn this stage the DUTinstance ofsuch as power and high-impedanceRegister settings that can not be altered during simulation0.80text
mode bits or portions of the environment registersVerification component settings that can not be altered during simulation ScoreboardDescriptionA scoreboard can be implemented in various waysinstance ofsuch as power and high-impedanceRegister settings that can not be altered during simulation0.80text
Universal Verification Methodologyrelated to OfficialUVM0.60section
Universal Verification Methodologyrelated to OfficialWorking Group0.60section
Universal Verification Methodologyrelated to OfficialAccellera18000.60section
Universal Verification Methodologyrelated to OfficialIEEE Standard0.60section
Universal Verification Methodologyrelated to OfficialUniversal Verification Methodology Language0.60section
Universal Verification Methodologyrelated to OfficialReference Manual0.60section
Universal Verification Methodologyrelated to OfficialIEEE0.60section

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