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In computer architecture, memory-level parallelism (MLP) is the ability to have pending multiple memory operations, in particular cache misses or translation lookaside buffer (TLB) misses, at the same time.
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citeseerx mlp ilp 10 parallelism superscalar time memory doi help cite computer ability multiple operations single often cache isbn uses
| Subject | Predicate | Object | Confidence | Src |
|---|---|---|---|---|
| the Intel Pentium Pro is five-way superscalar | instance of | e.g. a processor | 0.80 | text |
| with the ability to start executing five different microinstructions in a given cycle | instance of | e.g. a processor | 0.80 | text |
| but it can handle four different cache misses for up to 20 different load microinstructions at any time.It is possible to have a machine that is not superscalar but which nevertheless has high MLP.Arguably a machine that has no ILP | instance of | e.g. a processor | 0.80 | text |
| which is not superscalar | instance of | e.g. a processor | 0.80 | text |
| which executes one instruction at a time in a non-pipelined manner | instance of | e.g. a processor | 0.80 | text |
| but which performs hardware prefetching | instance of | e.g. a processor | 0.80 | text |
| Memory-level parallelism | related to References | Lock-green | 0.60 | section |
| Memory-level parallelism | related to References | Lock-gray-alt-2 | 0.60 | section |
| Memory-level parallelism | related to References | Lock-red-alt-2 | 0.60 | section |
| Memory-level parallelism | related to References | Wikisource-logo | 0.60 | section |
| Memory-level parallelism | related to References | Glew | 0.60 | section |
| Memory-level parallelism | related to References | MLP | 0.60 | section |
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