DDR5 SDRAM

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Support

Alder Lake Raptor Lake Raptor Lake Refresh Sapphire Rapids Meteor Lake

12 related topics

Overview

Synchronous dynamic random-access memory DDR4 SDRAM Bandwidth Ns Latency

16 related topics

Features

Error-correction code ECC memory Cache line X86

4 related topics

Memory modules

Capacitive Power management integrated circuit Passive components Voltage regulator modules

4 related topics

Key facts & relationships

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Bandwidth: 32.0–70.4 GB/s[a]
Clock rate: 2,000–4,400 MHz
Cycle time: 16n bank structure
Developer: JEDEC
Generation: 5th generation
Predecessor: DDR4 SDRAM (2014)

Topics to explore

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Overview

Synchronous dynamic random-access memory
DDR4 SDRAM
Bandwidth Bandwidth (computing)
Ns Nanosecond
Latency Memory timings
Dual in-line memory module DIMM
GT/s Transfers per second
Liquid nitrogen
Rambus
SK Hynix
JEDEC
Low Power Double Data Rate 5 LPDDR5
CUDIMM
ASRock
Intel
UEFI/BIOS

Features

Memory modules

Capacitive Capacitance
Power management integrated circuit
Passive components Passive component
Voltage regulator modules Voltage regulator module

Operation

Traditional RAS and CAS signals Dynamic random-access memory
LPDDR4 LPDDR

Support

Advanced semantic analysis

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Map overview Semantic statistics

Nodes44

Edges43

Triples30

Avg. degree1.95

Density0.045455

Components1

How this topic connects Entity context

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DDR5 SDRAM

Top relations

Standards · 15

DDR5 SDRAM → DDR5-4000 (PC5-32000), DDR5-4400 (PC5-35200), DDR5-4800 (PC5-38400), DDR5-5200 (PC5-41600), DDR5-5600 (PC5-44800), DDR5-6000 (PC5-48000), DDR5-6200 (PC5-49600), DDR5-6400 (PC5-51200), DDR5-6800 (PC5-54400), DDR5-7200 (PC5-57600), DDR5-7600 (PC5-60800), DDR5-8000 (PC5-64000), DDR5-8200 (PC5-65600), DDR5-8400 (PC5-67200), DDR5-8800 (PC5-70400)

related to External links · 3

DDR5 SDRAM → DDR4, JEDEC, Main Memory

Bandwidth · 1

DDR5 SDRAM → 32.0–70.4 GB/s[a]

Clock rate · 1

DDR5 SDRAM → 2,000–4,400 MHz

Cycle time · 1

DDR5 SDRAM → 16n bank structure

Developer · 1

DDR5 SDRAM → JEDEC

Generation · 1

DDR5 SDRAM → 5th generation

Predecessor · 1

DDR5 SDRAM → DDR4 SDRAM (2014)

Prefetch buffer · 1

DDR5 SDRAM → 4n

Release date · 1

DDR5 SDRAM → July 14, 2020; 6 years ago (2020-07-14)

Important terminology Word statistics

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Important terminology

ddr5 memory dimm ddr4 data higher modules support standard chip gt also one bandwidth bus 64 speeds sdram voltage chips

Entity relationships Subject–Predicate–Object triples

Subject	Predicate	Object	Confidence	Src
DDR5 SDRAM	Bandwidth	32.0–70.4 GB/s[a]	1.00	infobox
DDR5 SDRAM	Clock rate	2,000–4,400 MHz	1.00	infobox
DDR5 SDRAM	Cycle time	16n bank structure	1.00	infobox
DDR5 SDRAM	Developer	JEDEC	1.00	infobox
DDR5 SDRAM	Generation	5th generation	1.00	infobox
DDR5 SDRAM	Predecessor	DDR4 SDRAM (2014)	1.00	infobox
DDR5 SDRAM	Prefetch buffer	4n	1.00	infobox
DDR5 SDRAM	Release date	July 14, 2020; 6 years ago (2020-07-14)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-4000 (PC5-32000)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-4400 (PC5-35200)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-4800 (PC5-38400)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-5200 (PC5-41600)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-5600 (PC5-44800)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-6000 (PC5-48000)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-6200 (PC5-49600)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-6400 (PC5-51200)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-6800 (PC5-54400)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-7200 (PC5-57600)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-7600 (PC5-60800)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-8000 (PC5-64000)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-8200 (PC5-65600)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-8400 (PC5-67200)	1.00	infobox
DDR5 SDRAM	Standards	DDR5-8800 (PC5-70400)	1.00	infobox
DDR5 SDRAM	Successor	DDR6 SDRAM (planned 2028)	1.00	infobox
DDR5 SDRAM	Transfer rate	4.0–8.8 GT/s	1.00	infobox
DDR5 SDRAM	Type	Synchronous dynamic random-access memory	1.00	infobox
DDR5 SDRAM	Voltage	1.1 V nominal (actual levels are regulated by on-the-module regulators)	1.00	infobox

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