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Verilog

Verilog je jazyk pro popis hardware (HDL), slouží pro modelování a návrh elektronických systémů. Jazyk (někdy nazývaný Verilog HDL) podporuje design, verifikaci a realizaci analogových, digitálních a smíšených signálových obvodů s různou úrovní abstrakce.

Historie, Overview & Odkazy

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Autor
Phil Moorby, Prahbu Goel
Ovlivnil jazyky
SystemVerilog, Verilog-AMS
Ovlivněn jazyky
Pascal, Ada, C, Fortran
Paradigma
Strukturované programování
Poslední verze
IEEE 1364-2005
První oznámení
1984

Topics to explore

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Overview

Historie

Odkazy

  • ISBN International Standard Book Number

Advanced semantic analysis

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Map overview Semantic statistics

Verilog

Nodes31
Edges30
Triples35
Avg. degree1.94
Density0.064516
Components1

How this topic connects Entity context

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Verilog

Top relations

related to Historie · 17
Verilog → Accellera, Automated Integrated Design Systems, Cadence, Cadence Design Systems, Gateway, Gateway Design Automation, IEEE, Obyčejně, Open Verilog International, OVI, Philem Moorbym, Prahbu Goelem, Přenesla Verilog, Verilog-95, Verilog-XL, Verilogu, VHDL
related to Literatura · 6
Verilog → Brně, ISBN, Jazyk Verilog, Kolouch Jaromír, Nakladatelství VUTIUM, VUT
related to Verilog 2001 · 3
Verilog → IEEE, Některá, Verilogu-95
Autor · 1
Verilog → Phil Moorby, Prahbu Goel
Ovlivnil jazyky · 1
Verilog → SystemVerilog, Verilog-AMS
Ovlivněn jazyky · 1
Verilog → Pascal, Ada, C, Fortran
Paradigma · 1
Verilog → Strukturované programování
Poslední verze · 1
Verilog → IEEE 1364-2005
První oznámení · 1
Verilog → 1984
Přípona souboru · 1
Verilog → .v, .vh

Important terminology Word statistics

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Important terminology

jazyk jako design ieee modelování hdl hardware gateway později systémů verilogu známý 2001 2005 vhdl prahbu verze verifikaci analogových digitálních

Entity relationships Subject–Predicate–Object triples

SubjectPredicateObjectConfidenceSrc
VerilogAutorPhil Moorby, Prahbu Goel1.00infobox
VerilogOvlivnil jazykySystemVerilog, Verilog-AMS1.00infobox
VerilogOvlivněn jazykyPascal, Ada, C, Fortran1.00infobox
VerilogParadigmaStrukturované programování1.00infobox
VerilogPoslední verzeIEEE 1364-20051.00infobox
VerilogPrvní oznámení19841.00infobox
VerilogPřípona souboru.v, .vh1.00infobox
VerilogTypová kontrolastatická, slabá1.00infobox
Verilogrelated to HistoriePhilem Moorbym0.60section
Verilogrelated to HistoriePrahbu Goelem0.60section
Verilogrelated to HistorieAutomated Integrated Design Systems0.60section
Verilogrelated to HistorieGateway Design Automation0.60section

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    Min side: 3
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